Flash electrically programmable read only memories ("EPROMs") and flash electrically erasable and programmable read only memories ("EEPROMs") are solid state devices that can persistently store digital data. As shown by FIG. 1, an NMOS EPROM-type flash cell 10 typically has a metal-oxide-silicon ("MOS") semiconductor structure that includes an N-type source region 20 and an N-type drain region 30 formed on a typically P-type substrate (not shown), a floating gate 40 and a control gate 50. In a manner known to those skilled in the art, floating gate 40 is formed overlying a MOS channel region in the NMOS device substrate, but separated therefrom by a thin oxide layer. The control gate 50 is formed overlying the floating gate. In practice, the NMOS device substrate (or bulk) is coupled to a source of potential Vbb that typically is ground. (Of course a PMOS cell could be implemented by inter-changing P-type and N-type regions and substrate.) Although a flash-type EPROM cell has been described, high voltage generation according to the present invention may also be used with EPROM, or EEPROM type memory cells.
A Vcg voltage coupled to control gate 50 can affect charge stored on floating gate 40, which charge affects the Vt threshold voltage of MOS device 10. The magnitude and type of charge on the floating gate controls the minimum (or Vt) voltage Vcg that will turn-on device 10, causing drain-source current to flow across the channel region 20. (For example, if an erase operation were to drive too many electrons from the floating gate, too many holes would remain, depressing Vt below the memory cell's intrinsic value of Vt.) Device 10 is programmed to one of two states by accelerating electrons from the substrate channel region through the thin gate oxide layer onto floating gate 40. The state of device 10, e.g., how much charge is stored on floating gate 40, is read by coupling an operating voltage Vgs across source and drain regions 20, 30 and then reading the drain-source current Ids to determine whether the device is ON or OFF for a given control voltage level Vcg.
Hot electron injection is used to program a flash EPROM, but typically is impractical for erasing. Erasing is commonly done in blocks of cells, and would require relatively high current to be carried out using hot electron injection. During programming, it is necessary to apply a positive high voltage Vcg, e.g., perhaps +10 VDC to control gate 50, while applying perhaps +5 VDC to drain 30, and 0 VDC to source 20. As hot electrons are accelerated and travel from source to drain, the electric field created by the high Vgs and Vds voltages can pull some hot electrons from the drain to the floating gate. On the other hand, to erase a flash EPROM (or to program a flash EEPROM), it is necessary to apply a negative high voltage Vcg, e.g., perhaps -10 VDC, and a positive Vs or perhaps +5 VDC, while allowing Vd to float. The negative Vcg high voltage and Vs produce a large tunnel electric field that can push electrons from the floating gate 40 to the source 20.
Typically the circuitry with which memory cells 10 are used is powered by a single low voltage power supply, a 3.3 VDC battery for example, although lower or high voltage batteries may instead be used. Positive and negative high voltage pump circuits are commonly used to generate the .+-.10 V or so high voltage necessary to program and erase memory cells from a single lower voltage power supply. As will be described, the present invention is directed to providing positive high voltage using pump circuitry.
As shown in FIG. 2, it is common to form an integrated circuit ("IC") 100 that includes a plurality of cells 10 that are arrayed in addressable rows and columns that define a storage array 110. Address logic 120 permits accessing a specific cell in such an array. For example, during a program/read or erase operation, a given cell 10 may be accessed by applying the proper Vgs, Vd, Vs potentials via bit lines to all cells in a column containing the addressed cell, and via row lines to the row containing the addressed cell. For ease of illustration, address logic 120 is shown as having a single output lead, but in practice there will be multiple output leads, including leads for Vgs, Vd, and Vs.
As shown in FIG. 2, IC 100 (e.g., the circuitry thereon) preferably operates from a single low voltage power supply Vcc, which may be a battery especially if, for example, IC 100 is a storage unit within a laptop computer. Typically the low voltage power supply magnitude is 5 VDC or 3.3 VDC, although even lower voltages will be used in the future.
To generate the high voltage necessary to program or erase the various cells, IC 100 will include a positive high voltage pump circuit 130 that outputs a high positive potential VPout, and a negative high voltage pump circuit 140 that outputs a high negative potential VPout. IC 100 also includes a phase or clock generator circuit 150 that outputs a plurality of non-overlapping different phase pulse trains that drive the positive and negative pump circuits. High voltage pump circuits typically require two, and more commonly at least three-phase non-overlapping output pulse trains, e.g., .phi.1, .phi.2, and .phi.3 in FIG. 2. By non-overlapping it is meant that 0-to-1, and 1-to-0 voltage transitions of one phase pulse train should never overlap (e.g., coincide) with transitions of another phase pulse train.
In practice, positive high voltage circuit 130 may experience high current loading peaks when delivering high programming voltage to relevant bit lines. Adequately maintaining sufficient programming current while delivering the necessary high voltage presents a substantial challenge to circuit and device designers. One approach is to utilize larger-sized MOS devices and/or to parallel-couple the high voltage output from a plurality of high voltage pumps. However, such approaches tend to complicate the circuit design, and to require more IC chip surface area.
FIG. 3A shows a four-phase prior art four-stage positive high voltage charge pump circuit 130 such as might be used for circuit 130. In practice, however, high voltage generator 130 might include a number of such circuits whose VPout output nodes are coupled in parallel. Each circuit is termed four-phase because four drive non-overlapping clock signals, .phi.1, .phi.2, .phi.3, .phi.4, are used, as depicted in FIGS. 3B, 3C, 3D and 3E. Each circuit in FIG. 3A has four stages 140 that are series-coupled to provide the output voltage VPout. The magnitude of VPout will exceed the Vcc or E1 magnitude otherwise present in circuit 130. If outputs from multiple pump circuits 130 are parallel-coupled together, their drive clock signals must be properly sequenced to assure reasonable current distribution among the circuits.
In its simplest form, pump circuit 130 typically comprises native (e.g., very low threshold Vt) NMOS series-coupled charge transfer transistors M1A, M1B, etc., and associated AC-coupling capacitors C1, C2, C3, C4 (typically each a few pF), driven by clock signals .phi.1, .phi.2, .phi.3, .phi.4. It is the purpose of circuit 130 to increase (or pump-up) the voltage seen at node 1 successively by an AC-coupled magnitude that is proportional to magnitude E1 of the clock pulses, 3.3 V perhaps. It is the function of additional (preferably native) transistors M2 to decrease the Vt voltage drop from drain-to-source across each transistor M1.
Assume at first that devices M2A, M2B, etc. are removed, and that the gate and drain source leads of each device M1A, M1B, etc. are coupled together. (It is assumed that the source and drain regions of the various MOS devices disclosed in this application are in fact interchangeable.) The resultant configuration is analogous to series of PN diodes, in which node 1 is the anode lead and VPout the cathode lead.
Consider operation of the first transistor stage in the somewhat simplistic model under consideration. At time t1, a substantial fraction of the 0-to-1 transition (e.g., about E1 volts) of .phi.1 would AC-couple through capacitor C1 and elevate the potential at node 1. Node 1 would not receive 100% of the E1 transition, as there would be a voltage divider attenuation proportional to a ratio between C1 and the smaller magnitude equivalent shunt capacitance at node 1. But at 0 V gate-drain on M1A, there would be a Vt threshold voltage loss from drain to source across M1A, which would diminish the magnitude of the voltage increase (e.g., the charge transfer) seen at node 2. In similar fashion, the next series-coupled M1B transistor would AC-couple the 0-to-1 transition of .phi.3 to node 3 at time t5, elevating potential at node 3, but again suffering a Vt loss in the transfer of charge from node 2 to node 3.
Consider now the actual circuit 130 and the Vt cancellation function provided by transistors M2A, M2B, etc., whereby more voltage is transferred from drain to source across each coupling device M1A, M1B, etc. Reference is now made to the clock timing diagrams shown in FIGS. 3B-3E.
At time t0, .phi.4 transitions 1-to-0, coupling a negative voltage transient whose magnitude approaches El though capacitor C4 to the gate of devices M1B, M1D. These gate potentials are depressed down to a Vt below their respective source potentials, and M1B, M1D are turned-off. The off states of M1B, M1D will prevent backward charge flow (leftward direction charge flow, in FIG. 3A) when .phi.1 transitions 0-to-1.
At time t1, .phi.3 is high and the 0-to-1 .phi.1 state change begins a set-up transition that AC-couples a voltage transient approaching E1 through C1 to node 1 (and similarly to node 3). As a result, the quiescent M1A, M1C drain potentials elevate by about E1 volts. The gate nodes of M1A, M1C will each be at a potential of up to about Vt below their respective source nodes, e.g., nodes 2 and 4, and are thus off. Because M1A is presently turned-off, no charge transfers across M1A from node 1 to node 2, and because M1C is turned-off, no charge transfers across M1C from node 3 to node 4. Node 3, e.g., the gate node of M2B, is elevated positively by the t1 transient, which turns-on M2B. With M2B turned-on, M1B in the second pump stage remains off, as there is insufficient Vgs to turn-on. In the fourth pump stage, M1D also remains turned-off.
At time t2, the 1-to-0 transition of .phi.3 AC couples through C2 to depress potential at nodes 2 and 4. The gate potentials of M2A, M2C decrease, which turns-off devices M2A, M2C, leaving gate potentials of M1A, M1C unchanged. Assume that the negative-going time t2 .phi.3 transition brings nodes 2 and 4 below Vt less than the gate potential of M1A, M1C. Devices M1A, M1C begin to turn-on, and charge transfer can now start from node 1 to node 2 in the first pump stage, and from node 3 to node 4 in the third pump stage.
At time t3, .phi.2 transitions 0-to-1, AC-coupling a positive-going transient through capacitors C3 into the gates of devices M1A, M1C. These gate potentials elevate and devices M1A, M1C are turned-on even harder, to provide a more efficient charge transfer from nodes 1 to 2, and from nodes 3 to 4.
At time t4, .phi.2 transitions 1-to-0, AC-coupling a negative-going transient through capacitors C3 into the gates of M1A, M1C. Devices M1A, M1C turn-off, thus preventing any backward flow of charge (e.g., leftward in FIG. 3A) when .phi.3 transitions 0-to-1 at time t5.
During the transitions at times t5, t6, t7, the above-described charge transfer continues, except charge is transferred from node 2 to node 3, and from node 4 to Vpout.
Series-coupling several pump circuits 140 can further elevate the output potential from circuit 130. As noted in FIGS. 3C and 3E, gate clock signals .phi.2, .phi.4 to adjacent stages are substantially out of phase with each other.
In circuits operating with Vcc&lt;5 VDC or so, more than four pumping stages may be required to ensure outputting a sufficiently high magnitude VPout voltage. However, providing additional pumping stages and associated capacitors requires additional IC chip area that might otherwise be available for fabricating still more memory cells in array 130. Thus, it is important to transfer charge or voltage efficiently within individual pumping stages. As noted, the prior art circuit of FIG. 3A does not begin to really effectively transfer charge until time t3. Further, charge transfer efficiency is degraded by an inability to elevate gate potential at devices M1A, M1B, etc. sufficiently beyond associated source potentials.
Understandably it can be difficult to deliver sufficient magnitude VPout at required load current levels, while preserving the area on IC 100 required by high voltage generator circuitry 130 and its phase generator 150. As noted, it is possible to increase the available load current (i) provided to Cload, e.g., i=C.sub.load .delta.VPout/.delta.t, by summing together (e.g., parallel-coupling) the VPout output nodes from multiple circuits 130. However, ensuring a reasonable distribution of current among the individual circuits 130 can be challenging, and it is necessary to ensure properly timed sequential clock signals to the various circuits. In the prior art, such sequential timing is commonly achieved using fixed time delay circuits.
While this approach can work at a fixed master clock frequency, frequency variations can skew the sequence of clock signals, due to the non-varying fixed delays. The result can be that some circuits 130 are forced to deliver more load current than other circuits. It is important therefore to ensure proper device operation to avoid over-stressing MOS devices in any heavier-current circuits. Further, non-uniformity of supply current can result in the magnitude of VPout falling low enough to degrade memory array programming efficiency.
In summary, what is needed is a voltage pump circuit, e.g., to replace circuit 130, that can efficiently and reliably boost low voltage Vcc to high positive voltage, using fewer charge pump stages. Preferably such circuit should be implemented in a relatively small IC chip area, and should output V.sub.Pout reliably at required load current values, despite varying current demands imposed by storage array 110. Further, such circuit should lend itself to parallel output coupling, while promoting good current distribution among the individual circuits.
The present invention provides such a high voltage charge pump circuit.